The present invention relates to a method and apparatus for decoding coded data streams, including biphase coded data streams such as, similar to or compatible with the IEC 60958 and Japanese EIAJ CP-340 1987-9 standards. AES-EBU (Audio Engineering Society-European Broadcasting Union) and SPDIF (Sony Philips Digital Interconnect Format) are both implementations of the IEC 60958 standard.
Each of these standards is now widely used for digital audio transmission. These standards were developed following the introduction of the compact disc player in which digital audio data signals were initially retained inside the player cabinet and were converted to analogue signals before leaving the cabinet. However, audio (and now video) signals are increasingly maintained in their digital format for as long as possible to maintain digital quality. Thus, it is now common for digital audio and video data source devices, such as music synthesisers and CD, DVD, DAT and MP3 players to output the audio and video data in digital form to subsequent audio and video logic circuits. These logic circuits may be implemented in separate devices, such as desktop computers, amplifiers and televisions. The IEC 60958 standard was developed to aid transfer of digital signals between devices and has now effectively become the worldwide standard.
In common with other standards, the IEC 60958 standard uses biphase coding, such as biphase Manchester coding. In biphase coding, a data stream is combined with a clock on a single channel such that there are up to two transitions on the line for each data bit conveyed. Specifically, with biphase Manchester coding, there is a line transition at the end of each data bit period and a central transition if the bit is a ‘1’.
An example of biphase coding is shown in FIG. 1. Specifically, FIG. 1 shows an uncoded data signal in the middle, the data signal including a plurality of data bits. The clock for this data signal is shown above the data signal. The clock toggles or transitions from lo to hi at the start of each bit in the data signal. Thus, the clock includes a rising edge for every data bit. The corresponding biphase coded data is shown at the bottom of FIG. 1. Every data bit of the data signal is represented as two states in the biphase coded data, which each form a cell. Thus, the length of two cells is equal to the length of a data bit. Accordingly, where all flip-flops toggle on the same clock edge (for example, the rising edge), the clock required to produce the coded signal must have twice the frequency of the clock shown at the top of FIG. 1. As an alternative, it would be possible to use both clock edges to achieve the same effect. Such a clock is termed double data rate or double pumped. What is important, is that the clock provides two triggering events per data bit.
Since there is a transition at the end of each bit period in the biphase coded signal, the logical level at the start of a data bit is always inverted to the level at the end of the previous bit. In other words, the first cell corresponding to a bit in the biphase coded signal will always have a different state to that of the second cell of the preceding bit. Moreover, since there is a central transition if the bit is a ‘1’, the level at the end of a bit is equal (a ‘0’ transmitted) or inverted (a ‘1’ transmitted) to the start of the bit. This is sometimes termed biphase mark coding (BMC).
In the IEC 60958 standard, each audio frame contains two sub-frames. Each subframe contains one audio sample word. Such an audio sample word is a 32 bit word. In the IEC 60958 standard, the 32 bits in a subframe may be used as follows:
BitMeaning0-3Preamble4-7Auxiliary audio data bits 8-27Sample28Validity29Subcode data30Channel status information31Parity
Depending on the technology, different sample sizes are used in subframes. Thus, a 24 bit sample using bits 4-27 can be obtained. In contrast, a CD player uses only 16 bits so only bits 13(LSB)-27(MSB) are used. Bits 4-12 are set to ‘0’. However, it should be remembered that, when encoded, each ‘0’ bit includes a transition.
The number of subframes that is used depends on the number of channels that is transmitted, although no scheme is yet known that uses more than two subframes. If two channels are transmitted, then each frame contains two subframes and each of the two subframes contains a sample. The two subframe samples are played simultaneously on the respective channels. A block contains 192 subframes, numbered 0-191.
The sampling frequency (fs) is the frequency of samples in the data signal. Since two 32 words are transmitted for each sample, 64 bits are transmitted for each sample. Accordingly, the frequency of the clock shown in FIG. 1 is 64 times the sampling frequency (64 fs). Since two cells of are provided in the biphase coded signal for each data bit, the biphase coded signal clock frequency is 128 times the sampling frequency (128 fs).
Different technologies use different sampling frequencies. For example, for CD fs=44.1 kHz and for DAT fs=48 kHz. Accordingly, for CD 128 fs=5.6 MHz and for DAT fs=6.1 MHz. Thus, a block containing 192 subframes typically accounts for approximately 4 ms of audio (192/44.1 kHz=4.3 ms and 192/48 kHz=4 ms).
There are several technologies available for implementing digital to analogue converters (DACs), including R-2R ladders and constant calibration DACs. R-2R ladders are created from a network of precision resistors. Constant calibration DACs generate an output voltage by combining the charges of several capacitors, which are constantly re-calibrated. All DAC technologies have in common that they are expensive to manufacture. Accordingly, typical audio converters include DACs with less physical resolution than the 24 bit words containing the audio samples. Thus, to achieve the required resolution, an oversampling technique is used. In other words, the data is sampled at a multiple of the required sampling frequency fs and then filtered. These oversampling mechanisms are driven using a faster clock—that is, one running at a higher frequency. The audio clock of most audio converters therefore runs at 256 times the sampling frequency (256 fs), although higher frequencies such as 384 fs are known. As the received IEC 60958 signal carries the sampling clock fs in itself, the oversampling audio clocks are phase locked to the frequencies shown in FIG. 1.
As noted above, the first four bits (0-3) in each subframe form a preamble or header. The preamble thus contains eight cells and feasibly up to 8 transitions. The preamble is used for synchronisation and does not carry any audio data. Consequently, it does not use biphase coding. Thus, the preamble is capable of including more than two 0s or 1s in succession and always does so at the start to distinguish itself from the rest of the subframe. In practice then, the preamble never contains the 8 possible transitions.
In the IEC 60958 standard, the preamble forms one of three allowed synchronisation patterns, as follows:
Cell OrderPreambleLast Cell ‘0’Last Cell ‘1’B1110100000010111M1110001000011101W1110010000011011Preamble B marks a word containing data for channel A (left channel) at the start of the data block; preamble M marks a word containing data for channel A that is not at the start of the data block; and preamble W marks a word containing data for channel B (right channel), or any other channel except A.
Typical methods of decoding biphase coded data streams involve the use of analogue or digital phase locked loops (PLLs) to recover the biphase coded signal clock, which is at twice the bit rate or 128 fs. Typically, both types of PLL include, for example, a voltage controlled oscillator (VCO) generating a clock having approximately 128 fs. Transitions in the data stream are detected and low frequency transitions are filtered out so that only transitions at the approximate sampling frequency are retained. These transitions are used to adjust the phase and frequency of the clock generated by the PLL so that it matches the data clock of the written data. Thus, if the phase or frequency of written data changes, the PLL recognises these changes and adjusts accordingly. Once this data clock is recovered, it can be used to determine whether a transition has occurred between PLL clock cycles and hence to recover the proper stream of 0s and 1s in the encoded data. The encoded data can then be decoded using a reverse algorithm to the coding algorithm.
However, analogue PLLs suffer the drawback that they cannot easily be integrated with digital logic in typical application specific integrated circuits (ASICs), gate arrays and field programmable gate arrays (FPGAs). Digital solutions are therefore preferred. Unfortunately, digital PLLs also suffer a number of drawbacks, as discussed below.
The recovered IEC 60958 128 fs data clock rate is phase locked to the sampling frequency fs carried by the IEC 60958 signal. In addition, the oversampling frequency 256 fs for use in the audio converter must be created from the recovered IEC 60958 data clock. Thus, any jitter in the sampling frequency fs will degrade audio performance since aperture jitter (variations in the window during which a signal is sampled), bit resolution and signal-to-noise are inter-related. Clock jitter therefore audibly (or visibly) degrades the output of the audio (or video) output device. Typically, the AES/EBU standard for serial digital audio uses a 163 ns clock rate (or 6.1 MHz) and allows up to ±20 ns of jitter in the signal (equivalent to 50 MHz). Other standards are more stringent. Consequently, the jitter on the PLL data clock must be minimised to preserve audio fidelity. In other words, the window in which each rising edge of the clock transition may be generated must be minimised.
Improvements to biphase and other signal decoding therefore present a number of problems. First, it is desired to create a 256 fs clock with very little jitter to feed the audio (or other) system. In addition, it is desired to use the same clock to decode the incoming biphase coded data stream, such as an IEC 60958 or other coded signal, since this signal is phase locked with the signal output to the audio system. Thus, it must be possible to adjust this clock fast enough to track the phase jitter present in the biphase coded data stream, so that the bits can be consistently and accurately decoded. Moreover, the phase of the PLL must be set so that the centre of each cell in the biphase coded data stream is sampled. A fast PLL capable of tracking the IEC 60958 signal will have a wide lock range, but create a lot of jitter. In contrast, a stable PLL with low jitter will have a narrow lock range, but may not be fast enough to track the incoming IEC 60958 signal.
The usual approach for implementing the PLL clock would entail providing a fast free-running clock; using a programmable divider with a very high resolution; adjusting the programmable divider so that it follows or tracks the preambles; and using the (appropriately divided) output of the divider to decode the cells.
Unfortunately, there are several problems with this approach. In particular, this approach requires the phase reference to be determined by detecting preambles using a circuit running from the free-running clock. This means that the minimum obtainable error in the phase reference is dependent on the frequency of the free-running clock. More specifically, the minimum obtainable error decreases as the speed of the free-running clock increases. This phase reference error will effect the accuracy of the PLL and hence its ability to sample the centre of each cell in the biphase coded data stream. Thus, the accuracy of the clock generated by the PLL is limited by the accuracy of the phase reference and hence by the frequency of the free-running clock.
In addition, a digital PLL is a regulator, which controls the frequency of a programmable clock generator depending on the output of a phase comparator, which compares the phase of the generated signal with a phase reference. In this case, the phase reference is the phase of the detected preambles in the biphase coded signal. However, a simple P-type regulator will not be capable of tracking the digital signal with the required accuracy for this application.
It might be feasible to obtain the required accuracy using a PID-type regulator. Unfortunately, however, PID-type regulators introduce additional problems. In particular, PID-type regulators include arithmetic to control the clock signal. However, such arithmetic is slow and large when implemented in digital logic. In addition, there is a fixed relationship between the lock range and the accuracy of PLLs, which is dependent on the loop filter of the PLL. Thus, it is difficult to track different frequencies (for example, 44.1 kHz, 88.2 kHz etc for CD; and 48 kHz, 96 kHz etc for DAT) using a single set of parameters. Switching between different parameter sets requires further circuitry and is costly. Accordingly, implementation of the PLL using a PID-type regulator would be difficult at the required clock frequencies.
In summary, depending on the technology in which the apparatus is to be implemented, a PLL with the required clock speeds and accuracy is difficult to implement in a cost effective manner.